Semiconductor memory devices have undergone various design changes in terms of package density, operating speed, or power/current dissipation. Many devices, such as microprocessors, or other related devices include onboard memory components, which may contain one or more read only memory (ROM) cells.
ROM circuits are generally composed of memory elements disposed in rows and columns. Energizing the word-line corresponding to the desired word and also energizing the column corresponding to the addressed word generally address a particular word in a memory. There are schemes that can reduce static leakage and dynamic power consumption of the bit-line, for example, selectively pre-charging the bit-lines of a selected column.
FIG. 1, for example, illustrates a schematic diagram of a prior art “classical” NOR memory cell core 200. Cell core 200 demonstrates some of the problems with prior art architectures. Depending on the specifications, such prior art ROM configurations can offer high speed and high areas (e.g., NAND memory cell or special NOR memory cells), and may also offer low leakage, zero leakage, and low speeds. Some prior art configurations may also offer a medium area, a low speed, and low leakage. Such schemes, however, do not offer medium area, high speed, and low leakage (the disclosed embodiments do offer these features). The “classical” NOR memory cell core 200 configuration shown in FIG. 1 includes an arrangement in which WL <0, 1, 2, 3> are the word-lines and BL <0> is the column bit-line selected for the READ operation. A GND line can also be included with respect to the cell core 200. In general, no discharge takes place if, for example, WL 1 is selected. An accompanying timing diagram 20 is also shown in FIG. 1. The dashed area 28 shown in FIG. 1 indicates an overlapping of respective selected bit line pre-charge and word-lines 24 and 22. The scheme of circuit 200 shown in FIG. 1 suffers, however, from the problem of high dynamic power and high penalty on speed as the pre-charge is accomplished in the access time period, which overlaps with the word-line selection.
A need exists for ROMs that improve operational speeds while providing power and leakage benefits. As will be seen shortly, the disclosed embodiments can reduce leakage and power dissipation which offer continued high performance.